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VSD - Clock Tree Synthesis - Part 2

UPLOADER
Učlanjen(a)
01.05.2019
Poruka
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Bestseller | h264, yuv420p, 1280x720 |ENGLISH, 48000 Hz, 2channels | 4h 05mn | 424 MB

VLSI - Building a chip is like building a city!​

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What you'll learn

CTS Quality Checks (Skew, Power, Latency, etc.)

H-Tree

Quality Check of H-Tree

Clock Tree Buffering

Buffered H-Tree

H-Tree with uneven spread of Flops

Advanced H-Tree for Million Flops

Power Aware CTS (clock gating)

Static Timing Analysis with Clock Tree

Requirements

Individuals having Basic Knowledge of Electrical and Electronics

Description

This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis

Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop.

While we plan to add some expental videos and courses very soon, as a supplement, this one has real examples and problems that you see on a real chip, and even solutions to those problems

The course is structured in below format:

1) Introduction

2) Clock tree optimization checklist



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http://nitroflare.com/view/E86C3B6613B455D/EUl9NP8k__VSD__Clock.rar
 
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