Bestseller | h264, yuv420p, 1280x720 |ENGLISH, 48000 Hz, 2channels | 4h 05mn | 424 MB
VLSI - Building a chip is like building a city!
What you'll learn
CTS Quality Checks (Skew, Power, Latency, etc.)
Quality Check of H-Tree
Clock Tree Buffering
H-Tree with uneven spread of Flops
Advanced H-Tree for Million Flops
Power Aware CTS (clock gating)
Static Timing Analysis with Clock Tree
Individuals having Basic Knowledge of Electrical and Electronics
This course is a follow-up course of "VLSI Academy - Clock tree synthesis - Part 1". So its highly recommended to go through Part 1 of clock tree synthesis
Clock is a critical part of any VLSI chip, and this course takes you to the advanced level of building a clock tree from scratch for millions of flop.
While we plan to add some expental videos and courses very soon, as a supplement, this one has real examples and problems that you see on a real chip, and even solutions to those problems
The course is structured in below format:
2) Clock tree optimization checklist